.equ	PORTA	=0x1b
.equ	DDRA	=0x1a
.equ	PINA	=0x19

.equ	PORTB	=0x18
.equ	DDRB	=0x17
.equ	PINB	=0x16

.equ	PORTC	=0x15
.equ	DDRC	=0x14
.equ	PINC	=0x13

.equ	PORTD	=0x12
.equ	DDRD	=0x11
.equ	PIND	=0x10

.equ    UDR     =0x0c

.equ    MCUCSR  =0x34

; Set baud rate: 1000000 / (8 * 9600) -1
.equ    UBRRL   =0x09 ; uart delay
.equ    UBRRH   =0x20

.equ    UCSRA  = 0x0b
.equ      RXC     =7 ; 1: receive complete, data in udr
.equ      TXC     =6 ; 1: transmit complete
.equ      UDRE    =5 ; 1: udr is empty
.equ      U2X     =1

.equ    UCSRB  = 0x0a
.equ      RXEN    =4
.equ      TXEN    =3

.equ    UCSRC  = 0x20
.equ      URSEL   =7 ; 1: write to UCSRC, 0: write to UBRRH
.equ      UMSEL   =6 ; 1: asynchrone
.equ      UPM     =4 ; parity: 0=none, 2=even, 3=odd
.equ      USBS    =3 ; =0: 1 stop bit, =1, 2 stop bits
.equ      UCSZ0   =1

.equ    ADMUX  = 0x07 ; [ref1 ref0 adlar mux4 mux3 mux2 mux1 mux0]

.equ    ADCSRA = 0x06
.equ      ADEN = 7 ; enable ad converter
.equ      ADSC = 6 ; start conversion
.equ      ADFR = 5 ; free running mode
.equ      ADIF = 4 ; adc interrupt flag (conversion done)
.equ      ADIE = 3 ; interrupt enable
.equ      ADPS2 = 2 ; prescaler: 0=2, 1=2, 2=4, 3=8, 4=16, 5=32, 6=64, 7=128
.equ      ADPS1 = 1
.equ      ADPS0 = 0

.equ    ADCL   = 0x04
.equ    ADCH   = 0x05

; stack pointer
.equ    SPH     = 0x3e
.equ    SPL     = 0x3d

.equ    TWCR = 0x36 ; two wire control register, TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE
.equ      TWINT = 7 ; twi event occured (write 1 to clear)
.equ      TWEA  = 6 ; enable acknowledge
.equ      TWSTA = 5 ; start condition
.equ      TWSTO = 4 ; stop condition
.equ      TWWC  = 3 ; write collision
.equ      TWEN  = 2 ; enable twi
.equ      TWIE  = 0 ; interrupt enable

.equ    TWDR = 0x03 ; two wire data register
.equ    TWAR = 0x02 ; twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce
.equ       TWA0 = 1
.equ      TWGCE = 0
.equ    TWSR = 0x01 ; tws7 tws6 tws5 tws4 tws3 - twps1 twps0
.equ      START = 0x08
.equ      REPEATED_START = 0x10
.equ      MT_SLA_ACK = 0x18
.equ      MT_SLA_NOT_ACK = 0x20
.equ      MT_DATA_ACK = 0x28
.equ      MT_DATA_NOT_ACK = 0x30
.equ      ARBITRATION_LOST = 0x38
.equ      MT_SLA_R_ACK = 0x40
.equ      MT_SLA_R_NOT_ACK = 0x48
.equ      MT_DATA_IN_ACK = 0x50
.equ      MT_DATA_IN_NOT_ACK = 0x58
.equ      MT_SLA_W_ACK = 0x60
.equ      MT_SLA_W_NOT_ACK = 0x68
.equ      MT_STOP = 0xa0

.equ    TWBR = 0x00 ; two wire bit rate

.equ    TCCR1A = 0x2f
.equ       COM1A1 = 7 ; normal mode:    a1:a0, b1:b0 = 00 normal port, no modulation      01 toggle ocr1a/ocr1b on compare match
.equ       COM1A0 = 6 ;                                10 set low level on compare match  11 set high level on compare match
.equ       COM1B1 = 5 ; fast pwm mode:  a1:a0, b1:b0 = 00 normal port, no modulation      01 toggle oc1a, oc1b disconnected
.equ       COM1B0 = 4 ;                                10 high on bottom, low on cmpmatch 11 low on bottom, high on cmpmatch
.equ       FOC1A  = 3 ; force output compare oc1a
.equ       FOC1B  = 2 ; force output compare oc1b
.equ       WGM11  = 1 ; waveform generation, fast pwm 8 bit = 01[01], phase correct pwm 00[01]
.equ       WGM10  = 0 

.equ    TCCR1B = 0x2e
.equ       ICNC1  = 7 ; input capture noise cancel
.equ       ICES1  = 6 ; input capture edge select
.equ       WGM13  = 4 ; waveform generation, fast pwm 8 bit = [01]01, phase correct pwm [00]01
.equ       WGM12  = 3 ; 
.equ       CS12   = 2 ; 0 = no clock, 1 = clock, no ps, 2= ps8
.equ       CS11   = 1 ;
.equ       CS10   = 0 ;

.equ    TCCR2 = 0x25
.equ       FOC2  = 7 ; force output compare
.equ       WGM20 = 6 ; timer 2 wave generation mode bit 0
.equ       WGM21 = 3 ; timer 2 wave generation mode bit 1
                     ; 00 = normal, 01 phase-correct pwm, 10 ctc, 11 fast pwm
.equ       COM21 = 5 ; timer 2 compare match output mode bit 1
.equ       COM20 = 4 ; timer 2 compare match output mode bit 0
                     ; non-pwm: 00 = normal (port), 01 = oc0 on compare match, 10 = clear on compare, 11 = set on compare
                     ; fast-pwm: 00 = normal (port), 01 = reserved, 10 = set on bottom, clear on compare, 11 = clear on btm, set on compare
                     ; phasec-pwm: 00 = normal (port), 01 = reserved, 10 = clear when upcounting, set when downcounting, 11 = set when upcounting, clear when downcounting
.equ       CS22 = 2
.equ       CS21 = 1
.equ       CS20 = 0 ; 0=no_clock, 1=internal_clock, 2=8, 3=64, 4=256, 5=1024, 6=ext clock (falling edge), 7=ext clock (rising edge)


.equ    ICR1H = 0x27 ;Timer/Counter1 | Input Capture Register High Byte
.equ    ICR1L = 0x26 ;Timer/Counter1 | Input Capture Register Low Byte
.equ    TCNT2 = 0x24 ; Timer/Counter2 (8 Bits)

.equ    OCR1AH = 0x2b
.equ    OCR1AL = 0x2a
.equ    OCR1BH = 0x29
.equ    OCR1BL = 0x28
.equ    OCR2 = 0x23 ; Timer/Counter2 Output Compare Register

.equ    OCR0 = 0x3c
.equ    TCNT0 = 0x32
.equ    TCCR0 = 0x33
.equ      FOC0 = 7 ; timer 0 force output compare

.equ      WGM00 = 6 ; timer 0 wave generation mode bit 0
.equ      WGM01 = 3 ; timer 0 wave generation mode bit 1
                    ; 00 = normal, 01 phase-correct pwm, 10 ctc, 11 fast pwm
.equ      COM00 = 4 ; timer 0 compare match output mode bit 0
.equ      COM01 = 5 ; timer 0 compare match output mode bit 1
                    ; non-pwm: 00 = normal (port), 01 = oc0 on compare match, 10 = clear on compare, 11 = set on compare
                    ; fast-pwm: 00 = normal (port), 01 = reserved, 10 = set on bottom, clear on compare, 11 = clear on btm, set on compare
                    ; phasec-pwm: 00 = normal (port), 01 = reserved, 10 = clear when upcounting, set when downcounting, 11 = set when upcounting, clear when downcounting
.equ      CS02 = 2
.equ      CS01 = 1
.equ      CS00 = 0 ; 0=no_clock, 1=internal_clock, 2=8, 3=64, 4=256, 5=1024, 6=ext clock (falling edge), 7=ext clock (rising edge)

.equ    ACSR = 0x08

.equ    GICR = 0x3b

.def XL = r26
.def XH = r27
.def YL = r28
.def YH = r29
.def ZL = r30
.def ZH = r31

.equ    SFIOR = 0x30

.equ    SREG = 0x3f